Designing RF Transceivers in Extensively-Digital SoCs

Course 263

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Summary

Wireless consumer-market products, such as cellular transceivers, WiFi radios and Bluetooth devices, are being made available at ever reducing costs, while offering greater amounts of functionality and higher performance. This is made possible by increasing the level of integration and incorporating wireless transceivers with processors and other circuitry into a monolithic CMOS system-on-chip (SoC). In such environment, the transceiver architecture relies more heavily on digital logic and software algorithms when compared to traditional RF design approaches. This allows such SoC devices to leverage the benefits of the advanced nanometer CMOS fabrication processes while addressing the challenges associated with the implementation of RF functions in such environment. The constant introduction of new wireless standards, as well as the need to accommodate multiple standards in one platform, have made it necessary to adopt software-defined-radio (SDR) principles even in many consumer-market products.

This 3-day course presents the various aspects of this approach, including system-architecture, system and circuit level design methodologies, productization, and organizational aspects. The architectures covered include wideband/RF data converters, all-digital PLL, polar and quadrature digital transmitters, and digitally extensive techniques for efficiency enhancement in transmitters. Techniques for built-in calibration/compensation/testing in transceiver SoCs are highlighted as key elements in achieving cost effectiveness. Additionally, challenges associated with self-interference problems that are common in such integrated solutions, as well as techniques for the mitigation of self-interference effects, are also covered.

Learning objectives

Upon completing the course you will be able to:

  • Understand the general design considerations related with digital transceiver design
  • Become familiar with several extensively-digital implementations of wireless transceivers that have been recently demonstrated in digital CMOS processes
  • Select the most appropriate topology for a given wireless standard
  • Effectively partition hardware and software in a transceiver
  • Know the principles of operation of all-digital PLLs
  • Have a top-down approach to the formulation of technical specifications for data-conversion functions in a transceiver
  • Include productization aspects early in the design of a transceiver, allowing faster time-to-market and reduced productization costs
  • Offer multiple solutions for digitally-assisted built-in self-calibration and compensation techniques (self-healing) that address common impairments and are critically needed in cost-sensitive wireless transceivers
  • Avoid many self-interference problems and mitigate the effects of inevitable self-interference when it is experienced
  • Enhance the power-efficiency in digital transmitters

Target Audience

RF and baseband IC engineers, system architects, algorithm developers, test engineers, and product engineers.

Outline

Day One

Fundamentals of Digital-Radio Architectures
 • polar transmitters • quadrature transmitters • digital receivers •  analog/digital partition • hardware/software partition • software defined radios
The All-Digital PLL (ADPLL) and its use in Digital Transceivers
 • ADPLL versus conventional analog PLL • digitally-controlled-oscillator (DCO) • high-speed sigma-delta dithering for fine-frequency tuning •  time-to-digital conversion (TDC) as phase comparator • calibration/compensation in the ADPLL

Day Two

Examples of Digital Transmitters and Receivers
 • data-conversion considerations • digital solutions for data-conversion impairments • pulse-based transmitters (PWM/PPM) for complex modulation schemes
Techniques for Efficiency Enhancement in Transmitters
 • fundamentals of power efficiency in transmitters • envelope following versus tracking • extensively digital directions for supply modulation based transmitters

Day Three

Economical Manufacturability
 • built-in calibration and compensation (self-healing) • testing strategies and derived design specification • production-yield optimization and test-cost minimization
Designing for Self-Interference Mitigation
 • terminology and approaches • digital/software techniques for avoidance/mitigation of common self-interference mechanisms in receivers and in transmitters (e.g., parasitic modulation in LO resulting in spurs, receiver desensitization caused by clock harmonics)